Memory system using pipeline circuitry for improved speed
US4597061A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jan 3, 1983 |
| Grant date | Jun 24, 1986 |
| Priority date | — |
| Expiry date | Jan 3, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory apparatus including an array of storage elements connected to a plurality of addressing lines for selectively connecting a group of storage elements to a plurality of data lines. Control circuitry is also provided that is connected to the array for regulating the reading and writing of data to and from the data lines to the storage elements addressed by the address lines. A pipeline circuit is also provided that is connected to the address lines and to array of storage elements to store in response to the control circuit an address contained on the address lines. This memory system architecture allows for the address to be stored to allow the second address to be placed on the address lines while the first addressed data is being accessed from the memory array. This memory system also provides for the parity to be generated for the data in the array during the access of the data for the first address or after the pipeline circuit has been loaded with the second address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.