Architecture and method for testing VLSI processors
US4597080A · kind A · utility
51Cited by
4References
1Claims
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Key dates
| Filing date | Nov 14, 1983 |
| Grant date | Jun 24, 1986 |
| Priority date | — |
| Expiry date | Nov 14, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318547
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A method and apparatus for testing VLSI processors using a bit-sliced bus-oriented data path include data and control monitors and BIT for the on-chip memory. The data monitor is used to compress output data produced by the data path. BIT implementation of a functional test coupled with the data monitor are used for an off-line self-test of the data path in field. The control monitor is used to decouple the testing task of the control section from that of the data path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.