Computer memory apparatus
US4597084A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1985 |
| Grant date | Jun 24, 1986 |
| Priority date | — |
| Expiry date | Feb 4, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1637
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault-tolerant computer system provides information transfers between the units of a computing module, including a processor unit and a memory unit and one or more peripheral control units, on a bus structure common to all the units. Information-handling parts of the system, both in the bus structure and in each unit, can have a duplicate partner. The units of a module check incoming and outgoing signals for errors, signal other module units of a detected error, and disable the unit from sending potentially erroneous information onto the bus structure. Error detectors check the operation of the bus structure and of each system unit to provide information transfers only on fault-free bus conductors and between fault-free units. The computer system can operate in this manner essentially without interruption in the event of faults by using only fault-free conductors and functional units.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.