Modulo adder
US4598266A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Sep 24, 1984 |
| Grant date | Jul 1, 1986 |
| Priority date | — |
| Expiry date | Sep 24, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F7/729
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A modulo 2.sup.2n -1 adder employing adders which may all be standard binary adders. A first binary adder sums binary input signals a and b to produce a first sum signal in which the n+2 more significant bits represent the integer part of (a+b)/2.sup.2n (i.e., of a+b taken modulo 2.sup.2n). A second binary adder subtracts these n+2 more significant bits from a 2n bit shifted (less significant bits) version thereof for producing a first difference signal which is subtracted from the first sum signal in a third binary adder to produce a binary signal R. The signal R is applied to one input of a fourth binary adder which produces the desired modulo 2.sup.2n -1 signal. A comparator circuit applies a constant (2.sup.2n -1) to a difference input of the fourth binary adder only when R is greater than or equal to this constant.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.