Data processing system including a main processor and a co-processor and co-processor error handling logic
US4598356A · kind A · utility
23Cited by
7References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 30, 1983 |
| Grant date | Jul 1, 1986 |
| Priority date | — |
| Expiry date | Dec 30, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/0793
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system including a main processor and a co-processor, a logic circuit is coupled to receive error and busy outputs of the co-processor to generate an interrupt output on co-incidence of active error and busy signals and to latch the busy signal to the main processor to ensure that the main processor will honor the interrupt before executing another co-processor instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.