Analog switch circuit having output offset compensation circuit
US4599522A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 17, 1983 |
| Grant date | Jul 8, 1986 |
| Priority date | — |
| Expiry date | Nov 17, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/6872
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An analog switch circuit which is provided with a transmission gate consisting of a first n channel MOS transistor and a first p channel MOS transistor, which transistors are connected in parallel, wherein the output terminal of said transmission gate is connected to a second n channel MOS transistor and a second p channel MOS transistor, which transistors are supplied with an output voltage Vout from the transmission gate, and wherein mirror capacitances C.sub.mP12, C.sub.mP13, C.sub.mN12, C.sub.mN13 are provided at the output terminal of the transmission gate to offset a difference between the mirror capacitance C.sub.mN11 of the first n channel MOS transistor and the mirror capacitance C.sub.mP11 of the first p channel MOS transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.