Continuous data transfer system
US4599689A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Feb 28, 1983 |
| Grant date | Jul 8, 1986 |
| Priority date | — |
| Expiry date | Feb 28, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Apparatus controls sequential direct memory access (DMA) transfers between a plurality of buffer memories and a data translation device. Each buffer memory has an overrun area associated with it. Prior to transfers from the buffer memories to the data translation device, the buffer memories are first "threaded" together by loading the overrun area of a first buffer memory with data from the next buffer memory. During the DMA transfer, when the first buffer memory becomes empty a request is made to a computer to restart the DMA operation on the next sequential buffer, but while the request is being serviced, data is continually being transferred out of the first buffer's overrun area. Alternatively, for transfers from the data translation device to the buffer memories, after the first buffer memory is full, an interrupt is generated and incoming data is stored in the first buffer memory's overrun area while the interrupt is being serviced. After the interrupt is serviced, data is stored in the next sequential buffer memory in an area offset from the beginning thereof equal to the overrun area filled with data, the computer determining the exact point where the DMA process stopped de…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.