Semiconductor memory cell
US4601016A · kind A · utility
1Cited by
7References
22Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 24, 1983 |
| Grant date | Jul 15, 1986 |
| Priority date | — |
| Expiry date | Jun 24, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4113
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A high density, low power dissipating semiconductor memory cell is provided by connecting first and second inputs of a means for maintaining current in one of two conditions to first and second bit lines, by first and second diodes, respectively. Conveniently, the means for maintaining the current in one of two conditions includes first and second transistors operating in the normal current mode. Standby current is provided to the base of the first transistor through the first bit line and first diode, and to the base of the second transistor through the second bit line and second diode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.