PbS-PbSe IR detector arrays
US4602158A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 26, 1984 |
| Grant date | Jul 22, 1986 |
| Priority date | — |
| Expiry date | Oct 26, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10F39/1575
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A silicon wafer is provided which does not employ individually bonded leads between the IR sensitive elements and the input stages of multiplexers. The wafer is first coated with lead selenide in a first detector array area and is thereafter coated with lead sulfide within a second detector array area. The described steps result in the direct chemical deposition of lead selenide and lead sulfide upon the silicon wafer to eliminate individual wire bonding, bumping, flip chipping, planar interconnecting methods of connecting detector array elements to silicon chip circuitry, e.g., multiplexers, to enable easy fabrication of very long arrays. The electrode structure employed, produces an increase in the electrical field gradient between the electrodes for a given volume of detector material, relative to conventional electrode configurations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.