Multiplexed-access scan testable integrated circuit
US4602210A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 28, 1984 |
| Grant date | Jul 22, 1986 |
| Priority date | — |
| Expiry date | Dec 28, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318572
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A testable integrated circuit contains additional circuitry which defines--when operable in a test mode--a plurality of scan paths in each of which are connected in series a plurality of bistable elements (specifically, special scan path flip-flops) isolated from the integrated circuit combinational circuits. The input and output ends of these scan paths are connected by multi-level demultiplexer and multiplexer arrangements with the input and output pins, respectively, of the integrated circuit. The last level demultiplexer and the last level multiplexer include first groups of connections with the input and output ends of the scan paths, respectively, and second groups of connections with the input and output ends of the mission logic. The demultiplexers, the multiplexers and the scan path flip-flops are operable between mission and test modes upon the application of a mode control signal thereto. When the circuit is in the test mode, a test signal applied to the inputs of the scan paths is monitored at the output ends of the paths to indicate the correctness of operation of the SPFF's in each path. Composite test vectors are then applied for testing the combinational circuits vi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.