Management system for the memory of a processor or microprocessor

US4602328A · kind A · utility

Assignees

• L'Etat Francais represente par le Ministre des P.T.T. (Centre National d'Etudes des Telecommunications-CNET) · FR
• INSTITUT NATIONAL DE RECHERCHE EN INFORMATIQUE ET EN AUTOMATIQUE (INRIA) · FR

Inventors

• Ulrich Finger · Saalfeld, DE
• Pierre Ligneres · Antony, FR
• Ciaran O'Donnell · Paris, FR

Key dates

• Filing date: Dec 17, 1982
• Grant date: Jul 22, 1986
• Expiry date: Dec 17, 2002

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F12/0292
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system for the management of the physical memory of a processor which utilizes a base register which is loaded, for each virtual address of the memory, by a base address of a discriptive register corresponding to a task to be performed by the processor. This system utilizes a descriptive register table, an adder receiving the binary value of the base address of the first descriptive register, and the binary value of the index corresponding to the first register. The outputs of the adder address one of the inputs of the descriptive register table, thus selecting a segment descriptive register corresponding to the task to be performed. Each of the descriptive registers of the table contains control bits sent to the processor which makes it possible for the processor to check whether, for the segment to which the processor must have access, the processor must operate in the local or overall mode and whether the processor must process an input-output operation or an access to the memory.