Solder interconnection structure for joining semiconductor devices to substrates that have improved fatigue life, and process for making
US4604644A · kind A · utility
342Cited by
4References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 28, 1985 |
| Grant date | Aug 5, 1986 |
| Priority date | — |
| Expiry date | Jan 28, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10T29/49144
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An improved solder interconnection for forming I/O connections between an integrated semiconductor device and a support substrate having a plurality of solder connections arranged in an area array joining a set of I/O's on a flat surface of the semiconductor device to a corresponding set of solder wettable pads on a substrate, the improvement being a band of dielectric organic material disposed between and bonded to the device and substrate embedding at least an outer row of solder connections leaving the center inner solder connections and the adjacent top and bottom surfaces free of dielectric material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.