Buffer system for interfacing an intermittently accessing data processor to an independently clocked communications system
US4604682A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1982 |
| Grant date | Aug 5, 1986 |
| Priority date | — |
| Expiry date | Sep 30, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A buffer system for interfacing an intermittently accessing data processor to a communications system in which the transfer of data bits is clocked at a predetermined rate in response to clock pulses provided by a communications system clock signal. The system includes a random access memory (RAM) for storing input signal data bytes received from an input communications channel of the communications system and for storing output signal data bytes for transmission to an output communications channel of the communications system; and a port interface section that is responsive to the system clock signal for serially receiving and transmitting input signal data bytes from the input channel, for storing output signal data bytes to the output channel and for providing a flag signal to demarcate the data bytes. A transfer control signal generator responds to the flag signal by generating a sequence of transfer control signals for causing the RAM to store input signal data bytes from the port interface section, for enabling output signal data bytes stored in the RAM to be transferred to the port interface section, and for terminating the flag signal. The transfer control signal generator …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.