Pipeline error correction
US4604750A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Nov 7, 1983 |
| Grant date | Aug 5, 1986 |
| Priority date | — |
| Expiry date | Nov 7, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1048
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a data processing system, a memory (32) consists of data words and associated error-correction codes that are independently accessible; it is possible simultaneously to read a data word and write its associated error-correction code. This allows a memory-control circuit (30) immediately to store in the memory (32) a data word sent by a processor (10) while it is concurrently in the process of generating the error-correction code for that data word. The result is that the memory-control circuit (30) can subsequently fetch the newly stored data word before storage of its associated error-correction code is complete. This reduces delays involved in error-correction-code generation. The data word includes not only non-redundant information but also parity bits that both the processor (10) and the memory-control circuit (30) employ to determine whether a data word is correct. If the memory-control circuitry (30) determines that a word that it has forwarded to the processor (10) is incorrect, it immediately fetches the corresponding error-correction code and corrects the location in memory. Then, when the processor (10) finds that the parity is incorrect in the data word, it repeats i…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.