Error logging memory system for avoiding miscorrection of triple errors
US4604751A · kind A · utility
45Cited by
20References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Jun 29, 1984 |
| Grant date | Aug 5, 1986 |
| Priority date | — |
| Expiry date | Jun 29, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F11/1024
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Miscorrection of triple errors is avoided in a memory system equipped with a single bit error detection and correction/double bit error detection code by providing a double bit error logging technique. The address of each fetched word is logged in which a double bit error is detected. The address of each fetched word in which a single bit error is detected is compared with all logged addresses. If a coincidence is found between the compared addresses, a triple bit error alerting signal is generated and error recovery procedures are initiated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.