Differential pair amplifier enhancement circuit
US4605906A · kind A · utility
8Cited by
2References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jan 28, 1985 |
| Grant date | Aug 12, 1986 |
| Priority date | — |
| Expiry date | Jan 28, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/3211
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An enhanced differential pair amplifier circuit 28, 30 is described which provides a linearity correction technique. The linearity correction technique is designed to compensate for nonlinearities in the base-to-emitter output voltage of each transistor in a differential pair of transistors over the dynamic input range of the amplifier. The present invention comprises the inclusion of compensation diodes or transistors 42, 44 in the load circuit of each input transistor in the differential pair to compensate for nonlinearities.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.