Dual mode logic circuit for a memory array
US4608667A · kind A · utility
6Cited by
19References
12Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 18, 1984 |
| Grant date | Aug 26, 1986 |
| Priority date | — |
| Expiry date | May 18, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/086
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electronically selectable high performance data path switch which allows one input to drive two data buses or to have two inputs drive the two independently.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.