Semiconductor memory
US4608672A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 14, 1983 |
| Grant date | Aug 26, 1986 |
| Priority date | — |
| Expiry date | Jul 14, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device is provided which includes first and second memory arrays, each capable of storing data at locations therein, and an address decoder positioned between the first and second memory arrays for decoding address signals input thereto and corresponding to the locations. The address decoder is advantageously configured as a set of ISL gates or MESFET logic gates. It is further advantageous to form the memory arrays of Schottky diodes which, when employed with the ISL configuration for an address decoder, utilizes the same Schottky diode in the memory arrays as are utilized in the ISL gates. A further refinement provides a precharged circuit for each bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.