Method of manufacturing a memory FET with shorted source and drain region

US4608748A · kind A · utility

Assignee

• Tokyo Shibaura Denki Kabushiki Kaisha · JP

Inventors

• Hideo Noguchi · Tokyo, JP
• Tugunari Iwamoto · Kawasaki, JP

Key dates

• Filing date: Jun 18, 1982
• Grant date: Sep 2, 1986
• Expiry date: Jun 18, 2002

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10B20/00

Abstract

A method of manufacturing a semiconductor device having a plurality of MOS transistors which construct a memory section. After forming a plurality of MOS transistors on a semiconductor substrate, source regions and drain regions of given MOS transistors are shorted in accordance with a requested program. An insulating film is subsequently formed on the MOS transistors and an interconnection wiring layer is further formed thereon.