Programmable logic array device using EPROM technology
US4609986A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 14, 1984 |
| Grant date | Sep 2, 1986 |
| Priority date | — |
| Expiry date | Jun 14, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17716
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
An electrically programmable, eraseable and reprogrammable, monolithic integrated circuit logic array device is disclosed. The device includes a plurality of three types of logic array macrocells, each including an AND array matrix of EPROM transistors configured to form a plurality of "product terms" which are fed into another matrix comprised of "OR" gates, the outputs of which form sum-of-products expressions of the inputs to the AND arrays. Also contained in the macrocells are simple EPROM transistors which, when combined with other appropriate circuitry, form control elements, a plurality of storage registers (D flip-flops), feedback drivers, input drivers and output drivers, all integrated on the same substrate. The input drivers and feedback drivers provide input signals to the AND arrays and the outputs from the D flip-flops can be directed to either the feedback drivers or the output drivers. Control of data sources and destinations is determined by the control elements which in turn are determined by single EPROM transistors. Thus, the architecture as well as the logic function is programmable.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.