High speed fully precharged programmable logic array
US4611133A · kind A · utility
21Cited by
5References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 12, 1983 |
| Grant date | Sep 9, 1986 |
| Priority date | — |
| Expiry date | May 12, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1772
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A logic array which is small in size and low in power dissipation uses only one clock signal. The array is fully precharged by precharging a first portion and a second portion and then applying ground to the first portion while delayably applying the ground to the second portion. The address is read into the first portion during the precharging to speed up operation of the array.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.