DMA asynchronous mode clock stretch
US4611279A · kind A · utility
12Cited by
13References
4Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 14, 1983 |
| Grant date | Sep 9, 1986 |
| Priority date | — |
| Expiry date | Apr 14, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/282
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An adaptively stretched clock input feature is provided on a natively synchronous DMAC device to make it support data transfers in an asynchronous bus environment. This feature effects adjustment of the DMAC transfer strobe access window as a function of data transfer (DTACK) timing. A late DTACK signal causes stretch of the clock controlled TXSTB transfer strobe to a length which will accommodate worst case memory access conditions of the asynchronous bus structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.