Process for forming improved solder connections for semiconductor devices with enhanced fatigue life
US4611746A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 1984 |
| Grant date | Sep 16, 1986 |
| Priority date | — |
| Expiry date | Jun 28, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K3/3436
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
In accordance with the present invention, we provide a new method for relieving stresses in the device-substrate interconnection structure which greatly enhances the resistance of the interconnection solder bonds to fatigue failure. In accordance with the aforementioned object of the process of our invention for forming improved solder interconnections between integrated circuit semiconductor devices and the supporting substrate, the process includes the step of joining the device I/O pads to the corresponding I/O pads of the substrate by positioning the device over the substrate with solder material selectively positioned between the respective I/O pads, heating the assembly to at least the melting point of the solder material, and cooling to solidify the solder. Subsequently, the resultant device-substrate is annealed by heating to an annealing temperature in the range of 115.degree. to 135.degree. C. and maintaining this temperature for a time in excess of 2 days.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.