Process of fabricating three-dimensional semiconductor device
US4612083A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 1985 |
| Grant date | Sep 16, 1986 |
| Priority date | — |
| Expiry date | Jul 17, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/164
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A process of fabricating a three-dimensional semiconductor device, comprising the steps of preparing at least two multilayer structures each including at least one semiconductor element and a conductor connected at one end to the semiconductor element and having at the other end an exposed surface, at least one of the multilayer structures further including a thermally fusible insulating adhesive layer having a surface coplanar with the exposed surface of the conductor, positioning the multilayer structures so that the exposed surfaces of the respective conductors of the multilayer structures are spaced apart from and aligned with each other, moving at least one of the multilayer structures with respect to the other until the exposed surfaces of the conductors of the multilayer structures contact each other, and heating the multilayer structures for causing the insulating adhesive layer of at least one of the multilayer structures to thermally fuse to the other multilayer structure with the semiconductor elements electrically connected together.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.