Power transition write protection for PROM
US4612632A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Dec 10, 1984 |
| Grant date | Sep 16, 1986 |
| Priority date | — |
| Expiry date | Dec 10, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/225
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A power transition detection and override circuit is coupled to the OUTPUT-ENABLE (OE) pin of a nonvolatile electrically erasable programmable read only memory (EEPROM) for preventing inadvertent write commands thereto from a microprocessor arising from supply voltage (V.sub.cc) transitions, including power up and power down. With the EEPROM provided with internal write protection for V.sub.cc less than approximately 3.0 VDC, the power transition detection and override circuit holds the OE pin of the EEPROM low until V.sub.cc reaches a specified operating voltage, e.g., 4.75 VDC. This masks any WRITE ENABLE (WE) line glitches by the read operation of the active low OE line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.