Current compensation for logic gates
US4613772A · kind A · utility
19Cited by
6References
34Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Apr 11, 1984 |
| Grant date | Sep 23, 1986 |
| Priority date | — |
| Expiry date | Apr 11, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00361
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Current compensation for inverting logic gates is achieved by using a current mirror having a controlling leg equivalent to the input structure of the logic gate which is in the controlled leg. The controlling leg receives a reference voltage signal equal to the input signal to the logic gate which creates a leakage current. A plurality of controlled legs can be used with a single controlling leg to provide current compensation for a plurality of logic gates.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.