Laminated semiconductor assembly
US4613892A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Feb 19, 1985 |
| Grant date | Sep 23, 1986 |
| Priority date | — |
| Expiry date | Feb 19, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The problem of compensating for dimensional differences occuring in the length of adjacent stacks of semiconductors or other electronic components in an electrical assembly of such components is avoided through the use of a plurality of housing sections one for each stack with each housing section being comprised of stacked thin sheets of electrically conductive or electrically insulating material. Some of the sheets have cutouts to receive semiconductors. The stacks are tied together by ribbon-like flexible tabs integral with at least some of the sheets and interconnecting the housing sections. The tabs are constructed to be deformable generally independently of the other of the tabs.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.