Microprocessor including means for concurrently copying ALU results into selected operand register subsets and at least one main memory locations
US4615004A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Dec 13, 1984 |
| Grant date | Sep 30, 1986 |
| Priority date | — |
| Expiry date | Dec 13, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F15/786
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A microprocessor having a single common data bus (17) to which the output (33) of the arithmetic-logic unit (11) as well as input and output of the data memory (13) are connected without intermediate buffer registers. Of the working registers (21, 23, 25, 27) connected to the ALU inputs, one group (21, 23) is loaded from the common data bus and the other group (25, 27), used as accumulators, is directly loaded from the ALU output. Specific control circuitry (51, 53, 55, 57, 59, 61) allows selective storing of ALU output values into accumulators (25, 27), and simultaneous transfer with selective scaling into another register and into an addressed memory location within the same cycle during which the instruction was executed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.