Memory controller with synchronous or asynchronous interface
US4615017A · kind A · utility
65Cited by
7References
6Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 19, 1983 |
| Grant date | Sep 30, 1986 |
| Priority date | — |
| Expiry date | Sep 19, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4234
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A common memory interfacing circuit and method for coupling a memory to either a synchronous bus or an asynchronous bus. Synchronizing means are provided for synchronizing memory request signals with a local clock when the interfacing circuit is coupled to an asynchronous bus. The interface circuit responds to signals from the memory when internal memory operation has been completed and generates an acknowledge signal to send to the requesting bus. To simplify the common interface circuit, a synchronous protocol for information exchange between system components is made similar to an asynchronous protocol.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.