Microcomputer controlled data receiver
US4616314A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | May 12, 1983 |
| Grant date | Oct 7, 1986 |
| Priority date | — |
| Expiry date | May 12, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/04
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data receiver is described that includes a microcomputer that is coupled to a self-clocking asynchronous data bus. The data bus includes three signal lines TDATA, CDATA and RDATA. Bits of a data block are detected by a first exclusive-OR gate that is coupled to the TDATA and CDATA lines. An interrupt control signal and the output of the first exclusive-OR gate are coupled to a second exclusive-OR gate that generates an interrupt signal. The interrupt signal is coupled to the interrupt input of the receiving microcomputer. The receiving microcomputer is interrupted in response to a data bit and then changes the binary state of the interrupt control signal for producing an interrupt for the idle state between data bits. Upon being interrupted by the idle state between data bits, the receiving microcomputer changes the binary state of the interrupt control signal for producing an interrupt for the next data bit and also applies a bit of return data to the RDATA line. The received data block may include an address and a data portion.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.