Directory memory system having simultaneous write and comparison data bypass capabilities
US4616341A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1983 |
| Grant date | Oct 7, 1986 |
| Priority date | — |
| Expiry date | Jun 30, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F16/9017
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A directory memory system having simultaneous writing and bypass capabilities. A data output bit from a respective memory cell of a memory array is applied to a control input of a first differential amplifier, while comparison input data is applied to inputs of a second differential amplifier. The outputs of corresponding transistors of the two differential amplifiers are connected together. Current switch transistors, operated in response to a bypass select signal, supply current only to one or the other of the two differential amplifiers. The differential output signal produced across the commonly connected outputs of the two differential amplifier circuits is buffered and amplified with a push-pull output circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.