Semiconductor memory device
US4616343A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 16, 1985 |
| Grant date | Oct 7, 1986 |
| Priority date | — |
| Expiry date | Oct 16, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4094
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device including a random access memory cell array, a series/parallel data transfer circuit, transfer gate, an active pull-up circuit, and an active pull-down circuit. The transfer gate is inserted between bit lines of the random access memory cell array and the series/parallel data transfer circuit to carry out parallel transfer of data. Output data of the series/parallel data transfer circuit is simultaneously written in a group of memory cells of selected work lines by turning on the transfer gate and selection of a word line. When data of each output of steps of the series/parallel data transfer circuit is logic "1", the active pull-up circuit charges up a selected bit line of the random access memory cell array. When data of each output of steps of the series/parallel data transfer circuit is logic "0", the active pull-down circuit discharges a selected bit line of the random access memory cell array. One or more of the active pull-up and active pull-down circuits is arranged in the semiconductor memory device.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.