Static memory circuit
US4616344A · kind A · utility
15Cited by
6References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 29, 1983 |
| Grant date | Oct 7, 1986 |
| Priority date | — |
| Expiry date | Sep 29, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/419
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A static memory circuit includes memory cells arranged in a matrix of word lines and bit lines, and a reset circuit for resetting each pair of bit lines to have an equivalent potential in response to a change in a row address signal. The reset circuit generates a reset signal at a first time a certain time period after a first change of the row address signal and terminates the reset signal at a second time when a second change of the row address signal is detected. Thus, data destruction during reading is prevented.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.