Digital lock detector for a phase-locked loop
US4617520A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Jan 3, 1984 |
| Grant date | Oct 14, 1986 |
| Priority date | — |
| Expiry date | Jan 3, 2004 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S331/02
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A digital lock detector for a phase-locked loop accumulates out-of-lock pulses which are derived from a high frequency clock signal. The out-of-lock pulses are gated by an out-of-phase indicator signal and a pulse centered around the phase-locked loop output cycles to reduce the effect of relative phase jitter between the input and output signals of the phase-locked loop. The digital lock detector utilizes two counters in series which are reset independently to provide resistance to fading signal conditions. In addition, the lock detector circuit requires several consecutive long out-of-lock indications before an out-of-lock condition is indicated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.