Digital phase lock loop circuit
US4617679A · kind A · utility
42Cited by
7References
11Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Sep 20, 1983 |
| Grant date | Oct 14, 1986 |
| Priority date | — |
| Expiry date | Sep 20, 2003 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L7/0337
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital phase lock loop (PLL) circuit adaptable to a hard disk drive. The PLL operable at a high speed comprises a pulse shaper for subjecting raw data pulses from the disk drive to waveform-shaping, a phase comparator for producing a phase control pulse on the basis of the relative positions of a delayed reference clock (VCLK) pulse and each of said waveform-shaped data pulses from the shaper, and a phase shifter for generating the VCLK pulse in response to the phase control pulse.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.