Dual port access circuit with automatic asynchronous contention resolving capability
US4620118A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 1, 1982 |
| Grant date | Oct 28, 1986 |
| Priority date | — |
| Expiry date | Oct 1, 2002 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Two microprocessors, which may be operating asynchronously, share a random access memory (RAM) array; that is, at any one moment of time, either microprocessor can seek access to the RAM but only one of them can actually gain access at a time. Priority of access to the RAM is controlled by a dual port contention-resolving access circuit which enables such access alternately to the two microprocessors when both are seeking (overlapping) access, subject to the stipulation when neither microprocessor is accessing the RAM that the very next access will be allocated by the circuit on a first-come first-served basis, and will be allocated to a preselected one of the microprocessors if both microprocessors will commence to seek access precisely at the same time.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.