Dual-mode timer circuit
US4620119A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 6, 1984 |
| Grant date | Oct 28, 1986 |
| Priority date | — |
| Expiry date | Aug 6, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/04
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A dual mode timer circuit has first and second two-input NOR gates with inputs connected to receive a trigger pulse and outputs respectively coupled to first and second RC charging networks. An output NOR gate has its two inputs connected to the RC charging networks respectively, and its output connected to an output terminal. A control input voltage signal is coupled to a fourth NOR gate whose output is connected to control activation of the second RC charging network which has a shorter time constant than the first RC network. The output signal duration is dependent upon which RC network is effective. The output terminal is connected to the other inputs of the first and second NOR gates to render the circuit independent of trigger pulse duration.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.