Computer system

US4620275A · kind A · utility

Inventors

• Steven Jeffrey Wallach · Dallas, US
• Thomas M. Jones · Houston, US
• Frank J. Marshall · Plano, US
• David A. Nobles · Garland, US
• Kent Allen Fuka · Austin, US
• Steven M. Rowan · Garland, US
• William H. Wallace · Plano, US
• Harold W. Dozier · Carrollton, US
• David M. Chastain · Plano, US
• John W. Clark · Yarnton, GB
• Robert B. Kolstad · Dallas, US
• James E. Mankovich · Garland, US
• Michael Harris · Rochester, US
• Jeffrey H. Gruger · Dallas, US
• Alan D. Gant · Dallas, US
• Harold D. Shelton · Carrollton, US
• James R. Weatherford · Lake Dallas, US
• Arthur T. Kimmel · Dallas, US
• Gary Gostin · Plano, US
• Gilbert Hansen · Plano, US
• John M. Golenbieski · Dallas, US
• Larry W. Spry · Dallas, US
• Gerald Matulka · Carrollton, US
• Gaynel J. Lockhart · Richardson, US
• Michael E. Sydow · Carrollton, US

Key dates

• Filing date: Jun 20, 1984
• Grant date: Oct 28, 1986
• Expiry date: Jun 20, 2004

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F15/8069
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A vector processing computer is configured to operate in a pipelined fashion wherein each of the functional units is essentially independent and is designed to carry out its operational function in the fastest possible manner. Vector elements are transmitted from memory, either main memory, a physical cache unit or a logical cache through a source bus where the elements are alternately loaded into the vector processing units. The vector control unit decodes the vector instructions and generates the required control commands for operating the registers and logical units within the vector processing units. Thus, the vector processing units essentially work in parallel to double the processing rate. The resulting vectors are transmitted through a destination bus to either the physical cache unit, the main memory, the logical cache or to an input/output processor. In a further aspect of the computer there is produced an entry microword from a store for the immediate execution of the first microinstruction within a sequence of microinstructions. The remaining microinstructions are produced from a conventional store. This reduces the delay in the retrieval and execution of the first micr…