Integrated circuit redundancy and method for achieving high-yield production
US4621201A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Mar 30, 1984 |
| Grant date | Nov 4, 1986 |
| Priority date | — |
| Expiry date | Mar 30, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/00392
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit structure, and method for forming the structure, permits wafer scale integration by fabricating plural copies of the circuit in integrated circuit form, and interconnecting predetermined circuit element groups of the copies in a manner that permits a majority voting operation to take place. In this manner, defective circuit elements are masked by being out-voted by corresponding non-defective circuit elements that participate in the voting process. Alternate embodiments of a voter unit, used to implement the voting operation, includes a preferred embodiment that takes advantage of emitter-coupled-logic structure to provide a multiplex, voter, latch combination capable of selectively implementing normal and diagnostic operation. Included in the preferred embodiment of the voter unit is a fused link that implements a repair operation in the event there exists more defective circuit element groups than non-defective circuit element groups participating in the voting process.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.