CMOS adder using exclusive OR and/or exclusive-NOR gates
US4621338A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Apr 13, 1984 |
| Grant date | Nov 4, 1986 |
| Priority date | — |
| Expiry date | Apr 13, 2004 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3876
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
To implement CMOS EXORs or EXNORs, four transistors are used which have one end of their channels tied to the gate output. The first and fourth transistors are one conductivity type, and the second and third transistors are of the other conductivity type. One of the inputs is split up into two sub-inputs to which one of the digital signals has to be applied in uninverted form and in inverted form, respectively. The other end of the channel of the fourth transistor is connected to the first sub-input in the case of the EXOR and to the second sub-input in the case of the EXNOR. The reverse is true for the channel of the third transistor, while the channels of the first and second transistors are connected to the second input. The latter is also connected to the gates of the third and fourth transistors. The gate of the first transistor is connected to the channel of the fourth transistor, while the gate of the second transistor is connected to the channel of the third transistor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.