Process for the fabrication of a nonvolatile memory cell with very small thin oxide area and cell
US4622737A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Aug 12, 1985 |
| Grant date | Nov 18, 1986 |
| Priority date | — |
| Expiry date | Aug 12, 2005 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
On the doped area of a monocrystalline silicon substrate is grown a thick oxide layer a side portion of which is subjected to etching and underetching within a predetermined area until it uncovers an edge of silicon on which is then grown thin oxide; polycrystalline silicon layers separated by an oxide layer are then deposited to produce a nonvolatile memory cell in which the floating gate consisting of one of said polycrystalline silicon layers is separated from the underlying doped area of the substrate, which constitutes the drain, by a very small thin oxide area which adjoins an extended area of thick oxide. The electrical capacitance between the floating gate and the drain is thus reduced with resulting smaller dimensions of the cell for given performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.