Clock generator for providing non-overlapping clock signals
US4625126A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jun 29, 1984 |
| Grant date | Nov 25, 1986 |
| Priority date | — |
| Expiry date | Jun 29, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/1515
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
The non-overlap clock circuit of this invention is responsive to a variable input signal for producing a first and second output signal that vary respectively with phases opposite to and the same as the input signal. The circuit comprises a NOR-gate with its first input connected to the variable signal input and its second input to the second signal output of the circuit. The output of the NOR-gate is the first signal output of the circuit. The circuit includes a first means such as an enhancement type FET having a gate and a main current path. The gate is supplied with a first output signal of the circuit and the main current path is connected between ground and the second signal output of the circuit. A second means such as a depletion type FET is also employed with its main current path connected between the variable signal input and the second signal output of the circuit. The second signal output of the circuit is thus driven by the variable input signal through the main current path of the second means. The two output signals provided by the circuit do not overlap and will not simultaneously exceed a predetermined signal level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.