Dynamic memory refresh circuit
US4625301A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Nov 30, 1983 |
| Grant date | Nov 25, 1986 |
| Priority date | — |
| Expiry date | Nov 30, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/406
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit for generating refresh signals for a dynamic, random access memory is disclosed. The circuit comprises a timer which periodically generates refresh request signals. Each refresh request signal increments a refresh request counter. In normal system operation, after a memory access cycle, a refresh cycle is performed if there is a non-zero count in the counter. At the start of each refresh cycle, the counter is decremented and the refresh address to the memory is changed. Refreshing of the memory continues until the count is zeroed. If, for some reason, memory accesses are not performed within the memory refresh time limit, the count in the counter reaches a critical limit and a non-maskable interrupt is generated to the system processor causing it to access an interrupt vector in the memory and force refresh cycles.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.