Programmable array logic circuit with testing and verification circuitry
US4625311A · kind A · utility
23Cited by
5References
7Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 18, 1984 |
| Grant date | Nov 25, 1986 |
| Priority date | — |
| Expiry date | Jun 18, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/17708
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A field programmable array logic circuit is described wherein existing sensing circuitry is employed along with circuitry to enable every fuse location to be isolated, so that both a.c. and verification testing takes place under the same conditions, i.e. voltage levels and frequency, which occurs during normal operation of the programmed circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.