Dual edge clock address mark detector
US4625321A · kind A · utility
43Cited by
3References
1Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 23, 1985 |
| Grant date | Nov 25, 1986 |
| Priority date | — |
| Expiry date | May 23, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11B20/1419
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A circuit is disclosed for separating clock and data signals from a combined data-clock stream derived from a disk. The circuit includes two memories or shift registers which sample the incoming data at alternate portions of a reference clock. The outputs of the registers are applied to a decoder which identifies which of the two registers contains the data portion and which contains the clock portion with the missing clock pattern. That determination, in turn, controls the generation of the synchronization signal for the circuit and also establishes a control signal that selects data from the other of the registers.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.