Twin diode overvoltage protection structure
US4626882A · kind A · utility
Assignee
Inventors
Key dates
| Filing date | Jul 18, 1984 |
| Grant date | Dec 2, 1986 |
| Priority date | — |
| Expiry date | Jul 18, 2004 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/857
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Disclosed is an overvoltage protection structure which when used with CMOS circuits it protects them from overvoltage conditions while minimizing latch-up conditions in the structure. It consists of a well region of an opposite conductivity to that of the substrate defining a pocket region having a conductivity type which is similar to that of the substrate. A first PN junction diode is formed in a portion of the well region and a second PN junction diode is formed in the pocket region. The two diodes have opposite polarity and they both are connected to a signal line in such a way that one of the two diodes will be forward biased if the voltage on the signal line exceeds the bounds of the power supply voltages. The pocket region is connected to a V.sub.SS terminal which is normally grounded and the well region is connected to a power supply V.sub.DD. The doping concentration in the well region is predetermined to have a gradient so that minority carriers injected from one of the diodes in the well region will be repulsed and prevented from moving into the substrate region where they would be majority carriers and they could cause latch-up in the structure or at the very least adve…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.