Dual port memory word size expansion technique
US4627030A · kind A · utility
13Cited by
3References
5Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Feb 4, 1985 |
| Grant date | Dec 2, 1986 |
| Priority date | — |
| Expiry date | Feb 4, 2005 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1075
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An improved technique for word size expansion using dual port random access memories (DPRs) allows multiple integrated circuit chips to be used without introducing erroneous data. A master chip provides a signal derived from its conflict resolution circuitry to one or more slave chips. This prevents one or more chips in a word size expansion arrangement from selecting opposite ports when two access requests arrive simultaneously. An optional address latch input to the chips allows the retention of the same address hold time parameter for the expanded word as for a single DPR chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.