Integrated circuit structure comprising CMOS transistors having high blocking voltage capability and method of fabrication of said structure
US4628341A · kind A · utility
67Cited by
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2Claims
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Key dates
| Filing date | Sep 27, 1985 |
| Grant date | Dec 9, 1986 |
| Priority date | — |
| Expiry date | Sep 27, 2005 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S148/085
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit structure includes both low-voltage n-channel and p-channel MOS transistors (LV-NMOS transistors and LV-PMOS transistors) and high-voltage n-channel and p-channel MOS transistors (HV-NMOS transistors and HV-PMOS transistors). There are formed at the same time first p.sup.- regions for the compartments of the LV-NMOS transistors, second p.sup.- regions in which only the sources and channels of the HV-NMOS transistors are incorporated, and third p.sup.- regions in which only the drains of the HV-PMOS transistors are incorporated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.