Apparatus and method for synchronization of peripheral devices via bus cycle alteration in a microprocessor implemented data processing system
US4628445A · kind A · utility
11Cited by
8References
5Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Apr 7, 1986 |
| Grant date | Dec 9, 1986 |
| Priority date | — |
| Expiry date | Apr 7, 2006 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4217
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Synchronization of peripheral operation with that of a processor in a multi-microprocessor implemented data processing system is achieved by bus cycle alteration. A logic circuit is provided for monitoring the condition of a peripheral's status bits and for preventing an appropriate processor control signal from completing the present bus cycle if the peripheral of interest is not able to accept an access. The peripheral of interest is readily identified by providing unique memory mapped locations, one for each system peripheral, that are responsively connected to the logic circuit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.