Arrangement for optimized utilization of I/O pins
US4628480A · kind A · utility
Assignee
Inventor
Key dates
| Filing date | Oct 7, 1983 |
| Grant date | Dec 9, 1986 |
| Priority date | — |
| Expiry date | Oct 7, 2003 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/24
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Arrangement for the input of address data to an integrated circuit (IC) via the same input/output (I/O) terminal pins utilized for the transfer of data is disclosed. The I/O data pins each have an output data latch and an address latch connected to the respective pin and positioned internally of the circuit's interface. A logic level is applied to each of those I/O data pins via a respective external resistor for normally biasing the pin to that logic level. A further I/O pin at the circuit's interface is connected to a common conductor positioned externally of the interface. Diodes are connected between selected ones of the I/O data pins and the common conductor in accordance with a desired address. A level controller responds to a power-on-reset (POR) gating signal to switch the common conductor between a high impedance state and a logic level which effects conduction by the diodes, to enter address data bits. Address latches in the IC store the entered address data bits. The end of the gating signal enters the address bits into their respective latches. Output of data to the I/O data pins is via respective tri-stated transmit devices having their inputs connected to the outputs …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.